Generally, an integrated circuit (IC) of semiconductor devices (e.g., a diode and a transistor) is formed as a package, which is mounted on a printed circuit board (PCB). These packages have become smaller with the trend toward smaller-sized products. The Ball Grid Array package (hereinafter, referred to as ‘BGA’), which emerged in the early 1990's, has been widely used for high performance electronic equipment of different functions.
FIG. 1 is a cross sectional view of an example prior art BGA package. As shown in FIG. 1, a chip pad 102 and a bonding pad 108 are formed on a substrate 100. A chip 106 is bonded on the chip pad 102 of the substrate 100 by an epoxy adhesive 104. To provide an electrical connection between the substrate 100 and the chip 106, a wire bonding 110 is connected between the bonding pad 108 of the substrate 100 and a chip pad (not shown) of the chip 106. An epoxy-molding compound 112 is included in the package so as to protect the wire bonding 110. The chip package is then mechanically and electrically fixed to a printed circuit board (PCB) of a completed product by solder balls 114 formed on a lower surface of the substrate 100.
The prior art BGA package is fixed to the PCB by sequentially polishing a rear surface of a wafer, sawing the wafer into chips, bonding the chips, wire bonding, and molding.
In this BGA chip package, the substrate is connected with the chip by the wire bonding. This places a limitation on the small-sized package. Also, the fabrication process is very complicated, and it is not environmentally sustainable because it employs harmful pollutants such as the epoxy-molding compound. Also, the package is fabricated after sawing the wafer into chips.
However, a wafer level package (WLP) has recently been developed in which the IC package is formed before sawing the wafer into chips. This simplified method makes mass production possible. Furthermore, the plurality of chips arranged in a matrix-type configuration on the wafer are simultaneously fabricated, and are tested, so that it is possible to decrease the fabrication time and cost in the packaging and testing process for the IC chip.
Wood, U.S. Pat. No. 5,851,845, describes a wafer level package fabrication method wherein a rear surface of a wafer including a plurality of dies is thinned by grinding or etching, and a semiconductor package is formed by bonding the thin wafer to a substrate and sawing the substrate. Also, Sang Hoo Dhong, U.S. Pat. No. 6,221,769, describes a package fabrication method including mechanically forming a via-hole through a silicon substrate, and connecting the silicon substrate with a chip pad by the via-hole.
Furthermore, Korean Patent Publication. No. 2003-56174 describes a wafer level chip scale package (CSP) having no wire bonding wherein a conductive layer is formed on one surface of a chip, and a substrate having a conductive via-hole is bonded between a PCB and the chip. In this WLP method, instead of a prior art bonding method (wire bonding, TAB, flip chip bonding, etc.) between a chip and a package, a chip pad is connected with an external terminal by using a wiring method of a pre-semiconductor process before dicing in the same principle as that of the flip chip. However, this wiring method is very complicated, and requires an additional substrate provided between the chip and the PCB. Therefore, it limits the thinness of the completed product, and decreases the reliability of the chip.